Wireless SoC Design Engineer

**Role Number:** 200660318-3956

**Summary**

Come join Apple’s growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment and collaborating with people across different functional areas as well as thriving during crisis times, we encourage you to apply.

**Description**

Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with specified functional requirements. Engage in hardware/software partitioning discussions with software and firmware teams. Collaborate cross-functionally to ensure successful SoC integration, supporting design verification and validation across all phases—from concept to silicon bring-up. Work closely with physical design, DFT, and CAD teams to optimize performance, power, and area (PPA) targets while ensuring design quality and maintainability.

**Minimum Qualifications**

+ Bachelors Degree in EE,CE, or related field.

+ Knowledgeable about the ASIC design flow, including System Verilog RTL implementation.

**Preferred Qualifications**

+ Skilled in defining ASIC microarchitecture to meet functional requirements while managing performance, power, and area trade-offs.

+ Knowledgeable in Lint, CDC, RDC, Synthesis and STA.

+ Expertise in design domains such as memory subsystems, bus interfaces, CPU integration, DMA engines, Compression, Security IP design, and high-speed/low-speed peripherals like PCIE, QSPI, UART, and SPMI.

+ Thorough understanding of cross clock-domain design principles and associated CDC requirements.

+ Familiarity with ASIC low power design techniques, including multiple supply domains configuration, dynamic power/clock scaling, and power analysis.

+ Familiarity with ASIC test methodologies, encompassing DFT, scan insertion, memory BIST, and other related techniques.

+ Strong communication skills, both written and oral.