Microsoft Azure is building the fastest network in public cloud. We are seeking candidates who can span the stack from hardware to systems to applications, turning ideas into production systems at a rapid pace. Join us as a Senior Hardware Engineer to build the world's fastest public cloud and make a difference to millions of people across the planet.
As a developer in the network datapath FPGA team, you will be responsible for building, testing and deploying networking acceleration on Azure, and the largest deployment of FPGA SmartNICs in the world. You will develop the infrastructure for next-generation Software-Defined Networking (SDN), including arbitrary packet manipulations, reducing virtualization overhead, and improving performance with RDMA and custom network protocols. You should be able to drive projects with both hardware and software teams, and both inside and outside of Microsoft.
This is a unique opportunity for hardware developers to see their RTL code go to production within weeks instead of years. Come help build one of the few truly hyperscale global clouds with innovations possible at every level of the computing stack.
+ Design, propose and oversee the analysis/evaluation of hardware architectures
+ Design and code RTL modules written in Verilog / SystemVerilog and targeting FPGAs
+ Simulate and perform hardware-based testing, debug, and verification of FPGA designs
+ Scripting and basic software development in support of hardware design
+ Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment
+ Handle a DevOps role with occasional on-call responsibilities for resolving customer issues in production
+ 5+ years professional digital logic design, development, and verification experience
+ Experience in digital logic design and verification in Verilog, SystemVerilog, or VHDL highly preferred
+ Developing and deploying cloud applications for cloud hardware (NICs, GPUs, etc) highly preferred
+ Deep experience with FPGA programming including timing closure, resource management, and using IP libraries highly preferred
+ B.S, M.S, or Ph.D in Electrical Engineering, Computer Engineering or Computer Science
+ Strong knowledge of Verilog or SystemVerilog
+ Ability to read and write code in C, C++, C#, SystemC, Powershell and/or Python
+ Knowledge of networking fundamentals, including RDMA, SR-IOV, TCP, UDP, and IP
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:
Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form (https://careers.microsoft.com/us/en/accommodationrequest) .
Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.