ASIC Design Engineer - Pixel IP DMA

**Role Number:** 200660772-0836

**Summary**

Do you love creating sophisticated solutions to highly complex challenges? As part of our Hardware Technologies group, you’ll help design our next-generation, high-performance, power-efficient system-on-chips (SoCs). You will ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices!

In this highly visible role, you will be at the center of the Pixel IP design effort in pixel processing. You will collaborate with all teams, making a critical impact getting functional products to millions of customers quickly.

**Description**

As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that coordinate moving large amounts of data between the memory system and the Pixel IP Engine.

In this front-end design role, your tasks will include:
- Exploring solutions to enhance performance while minimizing power and area

- Detailing specifications and building RTL designs

- Working with design verification and formal verification teams to verify functionality and performance

**Minimum Qualifications**

+ Bachelors Degree + 0 years of experience

**Preferred Qualifications**

+ Experience in multimedia IP/SoC front-end ASIC RTL design

+ Tight-knit collaboration skills with excellent written and verbal communication skills

+ Experience working multi-functionally with architecture, design, and verification teams to specify, design, and debug designs

+ Previous experience designing dedication DMA engines (especially related to machine learning applications), data storage, memory controllers, networking, image processing, and/or interconnects

+ Good understanding of arbitration, address translation, caching, on-chip interconnects, and performance analysis

+ Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB)

+ Experience in front-end implementation tasks such as synthesis, area and power analysis, linting, and logic equivalence checks