+ Master's degree in Electrical Engineering or related field, or equivalent practical experience.
+ Experience developing compilers, loop transformations, scheduling, register allocation.
+ Experience in architecture performance analysis and optimization.
+ Experience developing complex software systems in C++1x. Proficiency in Python.
+ Knowledge of processor design and/or accelerator designs.
+ Knowledge of mapping machine learning models to hardware architectures.
+ Experience in analyzing workload performance and creating benchmarks.
+ Experience in hardware/software Codesign.
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services.
As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
Developing an Accelerator ASIC is a complex task that requires an understanding of Software workloads, pain points in execution, and effective partitioning of the workload between a general purpose machine and a hardware accelerator. To evaluate the benefits of hardware acceleration requires a combination of deep understanding of workloads, compilers, and target architecture.
As Architectural Performance Engineer, you will work with chip and compiler architects to profile workloads, analyze performance of the compiler and hardware using architectural models and silicon. You will also work with the team to build architectural models, prototype compiler optimizations, and define the next-generation Accelerator architecture.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
+ Work with ASIC and software architects to develop an architectural model for a hardware Accelerator, while also working closely with software and hardware teams on functionality, interfaces, and documentation.
+ Work with compiler engineers to analyze and optimize compiler code generation and prototype compiler optimizations in support of architecture exploration.
+ Contribute to the development of a shared modeling infrastructure with reuse, scalability as the goal.
+ Design experiments that enable the exploration of an architectural space for a given chip, collect and analyze the data, and inform the architectural choices made for a chip or system.
+ Correlate observed results from silicon with architectural model and refine/calibrate model.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy (https://careers.google.com/eeo/) and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing this form (https://goo.gl/forms/aBt6Pu71i1kzpLHe2) .