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SOC DFT Design Engineer

**Job Description**

We invite you to join Intel's Next Generation and Standards (NGS) Group and the 5G revolution. We are a global team of passionate engineers and technologists from diverse industry backgrounds, working together to realize a world of connected computing.

As a SoC DFT Design Engineer, you will be responsible for driving and execution of DFx design flow and implementations at block level and full chip level. You will be expected to be hands-on, use tools, participate in high-level silicon specifications, work closely with SoC architects and digital block leads to provide the best guideline for DFx technologies, and possess the skills to independently carry entire DFx flow toward the success of silicon tape-out/tape-in with world-class commercial quality.

Your responsibilities as a DFT Design Engineer will include, but not limited to the following:

+ Work with the digital design teams on understanding design in context of DFx implementations

+ Work with digital design team to initiate DFx architecture and TFM (Tools, flows, methodologies)

+ Develop new scripts/flows to improve DFx flow

+ Implement DFx solutions to SoC and deliver the best test coverage

+ Establish DFx simulation environment, and validate the DFx designs

+ Generate and deliver the test vectors to meet the requirements of state-of-the-art testers

+ The successful candidate must be a good team player with excellent interpersonal and communication skills

**Qualifications**

**Minimum qualifications:**

+ Bachelor's or Master's degreein Electrical Engineering or other related field of study with 7+ years of SoC DFx design experience.

+ 5+ years of ASIC development knowledge (pre-Si, post-Si).

+ 3+ years of scripting (PERL, Python) and debug analytic skills.

**Preferred Qualifications:**

+ Experience in DFT architecture design methodologies and CAD tools - SCAN, ATPG, JTAG, BSCAN and MBIST.

+ Experience in Pre/Post Si DFx (insertion, verification, coverage, debug) including production test vector generation.

+ Experience with design integration process.

+ Physical Design experience (DFx impact).

+ Experience with NOC AMBA LTE Bluetooth and/or other Physical layer WiFi SoC.

+ Experience with lab debugging, multi-team, multi-site working environment.

+ Experience with ASIC synthesis flows and working with physical design team.

**Inside this Business Group**

The Corporate Strategy Office is chartered to support the executive office in driving corporate initiatives, including near and long-term strategy, major cross-group decision making and ensuring cross-company alignment. To deliver to that mission, the team owns shaping, driving and synthesizing insights to directionally orient trends as well as long range strategic planning/visioning , cross company alignment and greenfield innovation. Communications are essential to drive alignment so there is a focus on communications, community and acumen development. The team is ccommitted to ensuring that Intel efforts are aligned to, and actively driving success toward the most impactful business strategies.

**Other Locations**

US, Arizona, Phoenix;US, California, San Diego;US, Texas, Austin

**Posting Statement**

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

SOC DFT Design Engineer

Full time
Santa Clara, CA

Published on 04/16/2021

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