SoC Physical Design Engineer
+ - You should have a minimum of 3-5 years of physical design experience, with recent successful tapeouts in deep submicron technology.
+ - Knowledgeable in partition level P&R implementation, including floorplanning, clock & power distribution, timing closure, physical & electrical verification.
+ - Proven understanding of PD construction & analysis flows and methodology.
+ - Shown ability to execute to stringent schedule & die size requirements.
+ - You should have polished social skills.
+ - Experienced in industry standard tools, understand their capabilities and underlying algorithms.
+ - Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ
- Work with logic design team to understand partition architecture and drive physical aspects early in design cycle. - Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. - Timing, physical & electrical verification, driving the signoff closure for the partitions. - Resolve design and flow issues related to physical design, identify potential solutions and drive execution.
**Education & Experience**
Bachelor’s degree or higher in Electrical Engineering, Computer Science, or related field.
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