Front End Design Engineer
Santa Clara Valley (Cupertino),California,United States
+ RTL Logic Design experience of multi-million gate ASICs.
+ Hands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies.
+ Experience writing specifications and converting them to design.
+ Experience with multiple clock domains and asynchronous interfaces.
+ Experience or knowledge of system architecture, CPU & IP Integration, and power and clock management designs desirable.
+ Ability to communicate effectively across all internal groups.
+ Familiarity with software and operating concepts a plus.
+ Familiarity with scripting languages like Perl, Python, or Tcl a plus.
As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: - Write microarchitecture and/or design specifications - Design, implement, and debug complex logic designs - Integrate complex IPs into the SOC - Support all front end integration activities like Lint, CDC, Synthesis, and ECO - Work with other engineers that are members of the SOC Design, SOC Design Verification, Emulation, STA, and Physical Design teams - Collaborate with software and systems teams to ensure a high quality end product
**Education & Experience**
BS or MS in EE, EECS, or CS is required.
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