PD CAD Engineer
+ Experience in P&R and flow development.
+ Understand various aspects of partition level PNR including floorplanning, power planning, placement, timing/power optimization, CTS, routing, UPF
+ Understanding and exposure to extraction and timing analysis flows
+ Understand hierarchical P&R issues is a key (top-level floor planning, pin-assignment, clock-distribution, UPF, power-distribution, multi-voltage design, pad ring construction, placement, optimization, and routing)
+ Strong scripting knowledge preferred.
+ Proven track record of managing, and regressing P&R flows.
+ You should be familiar with chip-finishing issues (metal-fill, spare-cells, DFM rules, boundary-cells, etc.) for the latest generations of process technologies.
+ We are looking for a self-motivated, dedicated problem solver. Strong interpersonal/communication skills are a requirement.
+ Innovus or ICC knowledge is a plus.
Provide innovative solutions to support and improve the quality of physical design. Work with chip design teams to implement and customize design flows that are optimal for a given chip Provide documentation, training, and new-user-support. Responsible for diagnosis, resolution, and regression of reported problems.
**Education & Experience**
BS/MS in EE/CS or equivalent.
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